1. Field of the Invention
The present invention relates to vertical MOS transistor and its production method, and particularly to a vertical MOS transistor having low ON-resistance and high withstand voltage at corners of a gate electrode of the transistor, and a method of producing such a vertical MOS transistor.
2. Description of the Prior Art
The vertical MOS transistor is one of promising devices that have high driving capacity and are compact on a substrate.
FIG. 1 shows a conventional vertical MOS transistor disclosed in Japanese Laid-Open Patent No. 1-192174. The transistor comprises an n.sup.+ -type semiconductor substrate 101, a drain region 103 made of n.sup.- -type impurity semiconductor grown epitaxially on the substrate 101, a channel region 105 made of p-type impurity semiconductor disposed in the drain region 103, a source region 107 made of n.sup.+ -type impurity semiconductor disposed on the channel region 105, a trench 123 formed through the source region 107, channel region 105 and drain region 103, a gate insulation film 109 formed over the surface of the trench 123, a gate electrode 117 disposed in the trench 123 on the gate insulation film 109, an insulation film 121 formed above the gate electrode 117, and a source electrode 119 formed over the insulation film 121. The gate insulation film 109 in the trench 123 forms a thick gate insulation film 129 on the bottom of the trench 123.
The vertical MOS transistor is advantageous in improving cell concentration, i.e., cell integration and reducing ON-resistance. The thick gate insulation film 129 on the bottom of the trench 123 is related to the depth of the trench 123 as well as the ON-resistance and withstand voltage of the transistor. Deepening the trench 123 may decrease the ON-resistance but deteriorate the withstand voltage. Namely, if the trench 123 is deepened to decrease the ON-resistance, it deteriorates the withstand voltage of the vertical MOS transistor. The thick gate insulation film 129 on the bottom of the trench 123 is to improve the deteriorated withstand voltage to a predetermined level (for example, a level that secures a 60-volt system).
FIGS. 2A to 2C are views showing a method of producing the conventional vertical MOS transistor of FIG. 1.
In FIG. 2A, the trench 123 is formed through the source region 107, channel region 105 and drain region 103. An oxide film 125 and a nitride film 127 are formed on the surface of the trench 123. The nitride film 127 is removed except on the side faces of the trench 123.
In FIG. 2B, the material is oxidized entirely with heat to thicken the oxide film 125, and the thick gate insulation film 129 is formed on the bottom of the trench 123 according to an LOCOS method.
In FIG. 2C, the trench 123 is filled with polysilicon to form the gate electrode 117. Thereafter, the source electrode 119, etc., are formed.
The vertical MOS transistor formed has the thick gate insulation film 129 on the bottom of the trench 123 to prevent an electric field from collecting at a part of the gate electrode 117, thereby improving the withstand voltage of the transistor.
If the gate insulation film 129 on the bottom of the trench 123 is thin, an electric field collects at corners of the gate electrode 117 in the trench 123 to deteriorate the withstand voltage, as is apparent from equipotential surfaces shown in FIG. 3.
Although the conventional vertical MOS transistor of FIG. 1 is effective to prevent the electric field from collecting to the corners of the trench, it has a problem.
Namely, in thickening the oxide film 129 on the bottom of the trench 123 in the thermal oxidation process of FIG. 2B, each corner 131 of the oxide film in the trench 123 forms a bird's beak shape as shown in FIG. 4. At this time, the nitride film 127 on each side of the trench 123 is pushed up to cause stress in the corner oxide film 131. As a result, the corner oxide film 131 dislocates to easily produce an electrical path at the corner, thereby deteriorating the withstand voltage. Namely, the conventional vertical MOS transistor of FIG. 1 still collects an electric field at each corner of the trench 123.
In addition, the nitride film 127 must entirely be removed from horizontal areas except on the side faces of the trench 123 according to an RIE method. This is very difficult to achieve because the selectivity of the RIE method is poor and because the side faces of the trench 123 are not always precisely vertical, thereby enhancing the risk of etching the nitride film on the side faces of the trench 123 also. This deteriorates a yield of transistors and the reliability of produced transistors. If the vertical MOS transistor has a V-shaped trench with inclined side faces, nitride films on the side faces will completely be etched away. This conventional method, therefore, is not applicable for such a V-shaped trench structure.